Nowadays, a digitally controlled converter system is widely favored because of its unique advantages such as advanced control algorithm, strong communication ability and high anti-disruption ability. The digitally controlled converter system comprises digital modules such as analog to digital converter (ADC) and digital pulse width modulator (DPWM). As shown in FIG. 1, generally, if the DPWM's resolution NDPWM is lower than the ADC's resolution NADC, or in other words, a voltage ΔVDPWM generated from a least significant bit (LSB) of a DPWM is larger than a voltage ΔVADC generated from a LSB of an ADC, the voltage difference between an output voltage Vo lead from a LSB of the DPWM and a reference voltage VREF will be larger than the minimum change ΔVADC that can be detected by the ADC. As a result, the system may fail to regulate the output voltage VO and the output voltage VO keeps oscillating around the reference voltage VREF. This phenomenon is called limit-cycle oscillation which may lead the output voltage VO to oscillate within a relatively large amplitude. It is hard to distinguish and compensate the noise disturbance from output voltage VO and the electro magnetic interference (EMI) from the converter system. Accordingly, the DPWM resolution NDPWM must be higher than the ADC resolution NADC n order to avoid the limit-cycle oscillation.
Generally, the DPWM structure is based on a counter. The DPWM resolution of this structure is related to the system clock frequency. Taking a counter-based DPWM in buck converter as an example, the output voltage generated by a LSB of the DPWM is:ΔVO=Vin·ΔD=Vin·fSW/fclock 
Wherein, Vin in is input voltage of the system; ΔD is the resolution of the duty cycle; fSW is the switching frequency of the buck converter; and fclock is the system clock frequency.
In the practical application field, the trend is more and more obvious that switching frequency is required to be high. Generally the switching frequency is higher than 500 KHz. Unfortunately, since the system cost will greatly arise if the system clock frequency fclock is higher than 200 MHz, the system clock frequency in the system is generally lower than 200 MHz. Hence, the output voltage ΔVO generated by a LSB of a DPWM is relatively high, or the DPWM resolution is relatively low. For an example, supposing the switching frequency fSW=500 KHz, the system clock frequency fclock=200 MHz, the system input voltage Vin=12V, then the output voltage ΔVO generated from a LSB of the DPWM is 30 mV. For a typical digitally controller converter system, the output voltage is relatively large and the corresponding DPWM resolution is relatively low.
Besides, the resolution of ADC is lower than the resolution of DPWM in order to avoid the limit-cycle oscillation. If the resolution of DPWM is low, the resolution of ADC should be correspondingly lower. A relative low resolution of ADC will worsen the performance of system transient response and affect the accuracy of the output voltage.
Accordingly, improved devices or methods are required to address the above deficiencies.